The present invention relates to formation of shallow trench isolation in a semiconductor device.
Semiconductor chips manufactured these days generally include millions of transistors. Isolation structures are provided between active regions of a semiconductor device. Each active region has a plurality of transistors and the isolation structures prevent short circuit from occurring among transistors provided in different active regions. As device size gets smaller, isolation between active regions within a semiconductor chip becomes more and more critical. Field oxide isolation is one common solution. With field oxide isolation, regions of oxide material are thermally grown to define active areas on the semiconductor chip. This technique requires considerable surface area and therefore is not desirable for highly integrated devices.
Another known solution is deep trench isolation, a technique where relatively deep trenches are filled with dielectric material and positioned between active regions. Unfortunately, forming reliable deep trenches is complicated and challenging, especially as spacing between devices get smaller. In addition, acceptable isolation is often not possible unless the depth of the trench is larger than the well depth.
Another isolation solution is the shallow trench isolation (STI) method, where a STI structure is formed to electrically isolate the two more active regions within a chip. The use of STI structure is advantageous in that it occupies a smaller area than the field oxide isolation and is easier to make than the deep trench isolation. Nevertheless, there are some fabrication problems or concerns associated with the STI. One such a problem is that a groove may be formed around the STI, resulting in uneven profiles that may cause current problems. This groove problem is particularly problematic for devices requiring thick gate oxides, e.g., devices having dual gate oxide layers. Another problem is that the thick gate oxide thickness on the STI corner is thinner than the plain region. This results in two oxide thickness on the STI corner is thinner than the plain region. This results in two problems: (1) the gate oxide quality degradation and (2) a leaky transistor, especially on NMOS. The electric field concentrates on a sharp corner region and causes the threshold voltage of the NMOS transistor to decrease partially in the STI corner region, which results in a sub-threshold leakage current, also referred to as a “double hump” problem.